Huawei unveiled its new chip design technology called Tau (τ) Scaling Law on May 25 at an IEEE symposium in Shanghai, aiming to enable chips with transistor density equivalent to 1.4 nanometers by 2031 [1, 2, 3, 4, 5]. Unlike conventional approaches that rely on shrinking transistor size, Huawei’s method focuses on reducing signal delay time and uses the LogicFolding architecture to achieve higher density without advanced lithography tools [6, 1, 2, 7, 4].

The company’s semiconductor chief, He Tingbo, said Huawei plans to start making 1.4-nanometer chips by 2031 using its own LogicFolding technology [8]. He added that improvements in lithography tooling—seen as a critical bottleneck in China’s chip industry—are “not necessary” under this new design path [7]. This approach aims to circumvent reliance on cutting-edge photolithography machines from suppliers like ASML, which remain off-limits due to US export restrictions imposed on Huawei since 2019 [8, 7, 9, 4].

Huawei has already designed and mass-produced 381 chips using the Tau Scaling Law over the past six years for applications including smartphones and AI computing [2, 4, 5]. Its Kirin smartphone chips featuring LogicFolding technology are expected to launch in fall 2026 [10, 4]. Despite China’s leading chip manufacturing capabilities currently around 7 nanometers, Huawei’s chip designs reportedly achieve much higher transistor density [1, 11]. Additionally, Huawei is collaborating with Nanjing University to develop a molybdenum disulfide-based microprocessor to push transistor integration further [11].

Industry leader Taiwan Semiconductor Manufacturing Company (TSMC) plans volume production of 1.4-nanometer chips by 2028, three years ahead of Huawei’s target [8, 1, 9, 4]. TSMC currently produces 2-nanometer chips but uses advanced lithography systems not available to Huawei.

Some analysts expressed skepticism over whether Huawei’s design innovations can fully overcome all manufacturing challenges seen at true 1.4-nm node sizes, such as yield, power consumption, thermal issues, and device performance. Paul Triolo of the DGA Group said that while stacked or folded designs can increase effective density, “it does not mean Huawei has solved the full process, yield, power, thermal, and device-performance problems associated with true 1.4 nm-class manufacturing” [10]. George Chen of The Asia Group noted this announcement may raise further concerns in Washington about Huawei’s ambitions under export controls [10].

Huawei aims to shift semiconductor progress from traditional Moore’s Law node shrinking to system-level time-scaling improvements using its new design law [2, 12, 4]. The next key milestone will be the fall 2026 launch of Kirin chips using LogicFolding technology for smartphones [10, 4]. Mass production of 1.4-nm-equivalent chips is targeted for 2031.